1. Field of the Invention
The present invention relates, in general, to a wireless data receiving device and, more particularly, to a divider circuit. This claims priority under 35 USC §119(e) (1) of Provisional Application No. 60/348,318, filed on Jan. 16, 2002.
2. Description of the Related Art
FIG. 5 is a block diagram showing a wireless data receiving device. Referring to FIG. 5, the wireless data receiving device comprises a filter/demod circuit 500 and an oscillating circuit 503. The filter/demod circuit 500 comprises a filter circuit 501 and a demodulated circuit 502. FIG. 6 is block diagram showing the oscillating circuit. Referring to FIG. 6, the oscillating circuit 503 comprises a phase comparing circuit 601, a low-pass filter (LPF) 602, a voltage-controlled oscillator (VCO) 603 and a divider circuit 604. FIG. 7 is a block diagram showing a conventional divider circuit using a binary counter. Referring to FIG. 7, the conventional divider circuit comprises D-type flip-flops (DFF) 700–703, inverter circuits 704 and 714, exclusive OR (XOR) circuits 705, 706 and 708, AND circuits 707 and 709–713 and a NAND circuit D15. The conventional divider circuit is a b 12th divider circuit. The conventional divider circuit has a four-bit counter and is a reset counter. The counter becomes zero after eleven (decimal number). D-type flip-flops 700–703 hold each bit value of the four-bit counter. Each of output signals D0–D3 output from D-type flip-flops 700–703 are the 2nd, 4th, 8th and 12th dividing signals, respectively. The signal D3 is used in the phase comparing circuit 601, but the other signals D0–D2 and D4–D15 are only used to generate the signal D3 in the conventional divider circuit. Except for the signal D3, every signal used in the conventional divider circuit might radiate from the conventional divider circuit and may become a noise signal in peripheral circuits.
Next, that signals in the conventional divider circuit become noise will be described with reference to the following example. FIG. 8 is a timing chart for explaining the operation of FIG. 7. In this example, the filter circuit 501 only passes the signal which has frequency components from 1.5 MHz (megahertz) to 2.5 MHz and cuts off the signal which has frequency components outside of the range. Also, in this example, the conventional divider circuit has input thereto the signal having frequency components of 12 MHz. The signal D0 having a frequency component of 6 MHz, the signal D1 having a frequency component of 3 MHz, the signal D2 having a frequency component of 3 MHz, the signal D3 having a frequency component of 3 MHz, the signal D7 having a frequency component of 6 MHz and the signal D9 having a frequency component of 6 MHz are outside of the passing band of the filter circuit 501. The filter circuit 501 cuts off these signals. Therefore, these signals do not become noise signals having a bad effect on system. On the other hand, the signal D2 having a frequency component of 1.5 MHz, the signal D3 having a frequency component of 1.5 MHz and the signal D7 having a frequency component of 2 MHz are inside of the passing band of the filter circuit 501. So, when these signals are input to the filter circuit 501, the filter circuit 501 passes these signals to later circuits. Therefore, these signals become noise signals. So, the passed noise signals have a bad effect on system.